1. Field of the Invention
The present invention relates to a level converter, and in particular to a level converter for an inverter. More particularly, the present invention relates to a level converter for a CMOS inverter that can sufficiently raise an insufficient amplitude input signal to a prescribed amplitude of the signal for the inverter.
2. Discussion of Background
A CMOS inverter is usually made by coupling a p-channel MOS transistor or an n-channel MOS transistor such as shown in FIG. 6. This circuit operates as an inverter during an ON state of either one of the two CMOS inverters P10 and N10. However, such a CMOS inverter has problems and defects. In particular, a problem exists concerning a pass through current that flows from the power source Vcc to the ground GND due to a phenomenon that both of the CMOS transistors P10 and N10 are in an ON state at the same time. Such a phenomenon occurs when the ON state of either one of the two CMOS transistors is changed to the OFF state, or vice-versa, due to supplying an input signal with an insufficient amplitude. This phenomenon frequently occurs due to a structure of a preceding stage to the input of the inverter.
For instance, as shown in FIG. 6, assume that a high level of the CMOS inverter is 5 V as a power source Vcc, and a low level of the inverter is 0 V as a ground GND. In addition, assume a gate-source operational threshold voltage Vthn of the n-channel MOS transistor N10 is approximately 0.8 V.
In such an operational condition for the CMOS inverter, assume an input signal with an insufficient amplitude of a voltage is supplied to the inverter. As shown in FIG. 6, the input signal has reached only 4 V as the high level and 1 V as the low level. If one of the CMOS transistors begins to operate under these insufficient conditions, the input level of the inverter can only reach 1 V. Further, the gate-source voltage VGS of the n-channel MOS transistor N10 becomes 1 V (i.e., 1 V-GND (0 V)). Accordingly, the gate-source voltage VGS becomes higher than the gate-source operational threshold voltage Vthn of 0.8 V. When the n-channel MOS transistor N10 is in the ON state, the p-channel MOS transistor P10 is also in an ON state, since the input level of the p-channel MOS transistor P10 is also at a naturally low level. Therefore, since both of the CMOS transistors are in the ON state at the same time, a pass through current flows through the inverter in the direction from the power source Vcc to the GND. Similarly, the pass through current flows when the input level of the inverter changes from the low level to the high level.
To prevent an occurrence of the pass through current, a level converter for the inverter has been proposed. As illustrated in FIG. 7, a conventional level converter for the inverter includes an inverter INV-A1 and two diodes D1 and D2 that are respectively coupled to the respective sides of the power source and the ground for the inverter INV-A1. In addition, a positive feedback circuit including inverters INV-B1 and INV-C1 is connected to the output of the inverter INV-A1.
In the level converter shown in FIG. 7, by means of a forward voltage of the diode (hereinafter referred to as VF), the inverter INV-A1 provides a high level output signal of (Vcc-VF) and a low level output signal of (GND+VF) when an input signal (in) is supplied. The circuit including the two inverters INV-B1 and INV-C1 converts the output signal of the inverter INV-A1 to the high level of the source voltage Vcc or the low level of the ground voltage GND by a toggle operation of the positive feedback circuit.
FIG. 8 explains the operation of the conventional level converter. Assume that, as explained in FIG. 6, the input signal to the inverter INV-A1 only reaches the low level of 1 V. Supposing that a drop of the forward voltage of the diode D2 is about 0.7 V, the gate-source voltage VGS of the n-channel MOS transistor N11 becomes about 0.3 V (i.e., 1V-0.7- GND (0)). Since the gate-source voltage VGS of the n-channel MOS transistor N11 becomes lower than the gate-source operational threshold voltage Vthn of 0.8 V, the n-channel transistor N11 is in an OFF state. At this time, the p-channel MOS transistor P11 is in an ON state, since the low level signal is supplied to the input (in). Consequently, the occurrence of the pass through current through the inverter INV-A1 is prevented. Similarly, when the high level input is supplied, the occurrence of the pass through current through the inverter INV-A1 is also prevented or suppressed.
In addition, by means of the positive feedback circuit including the inverters INV-B1 and INV-C1, the insufficient low level output of 0.7 V from the inverter INV-A1 is converted to the sufficient low level of 0 V. Similarly, when an insufficient high level of the input signal is supplied to the inverter INV-A1, the output is converted to the sufficient high level of the power source voltage Vcc (5 V).
As mentioned above, the occurrence of the pass through current through the inverter INV-A1 is prevented and a sufficient amplitude of an appropriate amplitude range is accomplished in the conventional level converter shown in FIG. 7. However, a defect exists because a pass through current is generated during the level transition from a high level to a low level, or vice versa. That is, when the level transition occurs, an output short circuit occurs between the inverter INV-A1 and the inverter INV-C1 as shown in FIG. 7 by a dotted line. Accordingly, it is still impossible to avoid wasting current through the inverter.
FIGS. 9A and 9B explain an operation of the level converter shown in FIG. 8 for the case of the level transition discussed above. As shown in FIG. 9A, the input level (in) to the inverter INV-A1 transfers from a high level of Vcc-VF to a low level of VF. Namely, the input level of the inverter INV-A1 is at the high level (Vcc-VF) at an initial state. In this state, an output level of the inverter INV-A1, an input level of the inverter INV-B1, and an output level of the inverter INV-C1 are equally at a low level (GND). Further, both the output of the inverter INV-B1 and the input of the inverter INV-C1 are kept at the high level of Vcc at the initial state.
The input (in) level starts to transfer at time t1, and when it falls to 1/2 Vcc at time t2, the output of the inverter INV-A1 (A1 out) rises and a level begins to invert. When the output (A1 out) of the inverter INV-A1 reaches 1/2 Vcc at time t3, the output of the inverter INV-B1 begins to invert. When the output of the inverter INV-B1 falls to a prescribed level at time t4, the inverter INV-C1 begins to invert. Next, when the input (in) reaches VF at time t5, the output of inverter INV-B1 reaches the low level (GND) at time t6 due to the positive feedback function.
In other words, when the input (in) of the inverter INV-A1 changes from a high level to a low level, so that the output rises from a low level to a high level, a pass through current is generated in the inverter INV-B1, and its output is supplied to the inverter INV-C1. Due to this, in the inverter INV-C1, both a p-channel and an n-channel MOS transistor become conductive.
Consequently, as indicated by the dotted lines in FIG. 8, a pass through current flows from the power source to the ground GND through the p-channel MOS transistor in the inverter INV-C1 and the diode D2. The condition of the pass through current is hereinafter referred to as "pass through mode".
FIG. 9B illustrates a current waveform due to the pass through mode. The output of the inverter INV-A1 moves towards the high level, and its output collides with the output of inverter INV-C1 due to the pass through mode. In this way, the output of the inverter INV-A1 and the output of the inverter INV-C1 collide with each other. Consequently, a power is wasted due to a wasteful current during the pass through mode. It also affects the output level, so that an appropriate CMOS level cannot be realized.
In order to eliminate the wasteful current by preventing the occurrence of the pass through mode, it is necessary to set a lower driving power of the inverter INV-C1 on the feedback side. However, when this setting is made, the timing for reaching the full output of the amplitude becomes slower.
As explained above, the conventional level converter has problems when the input level transfer from a high level to a low level. That is, current is wasted due to the pass through mode in a positive feedback circuit.
Also, as explained in FIG. 6, the conventional inverter has a defect of a "pass through current" that flows from the power source to the ground when the input changes from an ON state to an OFF state or vice versa, which causes both channel MOS transistors P10 and N10 to be in an ON state.